LOGIC CIRCUIT

Electrical/Electronic Engineering - Logic Circuit



HNC Diploma Electrical/Electronic Engineering - Logic Circuit

Introduction 

In this paper we are going to discuss the basic differences between the CMOS and TTL technologies. A deta8iled comparison of these two technologies has been made with special importance given to Quad two input NAND gate. We are also going to discuss the two technologies in terms of their thermal abilities such as fan out delay of propagation and speed of switching, operating voltage and power dissipation of the two technologies. We also going to compare the two technologies using the data sheets provided by the manufacturers for a NAND gate of quad two input. We will also describe the operation of sequential logic devices and the working of JK and D type fillip flop in a detailed prospective. We will also demonstrate that how a 4 bit shift register can be implemented using JK and D flip flop.

Discussion

Criteria 1

Differences between CMOS and TTL signals

CMOS family characteristics

They have a very low value of power dissipation in comparison to the other TTL logic family of the integrated circuits. The power dissipation of IC based on number of different factors such as the vo0ltage of the power supply, load at the output terminal, frequency of the operating signal and the rise time of the input. At the frequency of 1MHz and a capacitive load of 50 pF the power dissipation of CMOS logic is 10 nW per gate.

They have extremely short delay of propagation of signals and is highly dependent on the voltage supplied to them. These delays in propagation are usually in the range of 25 nS to 50nS.

The rise and fall time of CMOS logic gates can be controlled. They are usually the ramp functions instead of step and are approximately 20-40% longer then the delay of propagation.

The immunity to noise tends to 50% to 45% for an entire logic swing.

Due to the high input impedance, the levels of logic signals are equal to the power supplied since the impedance of the input is too high.

TTL family characteristics

The dissipation of power is generally 10 mW per gate which is significantly higher than CMOS family.

The delay of propagation is 10nS when having a load of 15 pF/400 ohm.

The levels of voltage varies from 0 to Vcc is usually 4.75 to 5.25v. The voltage ranges from 2V to Vcc produce a logic level 1.

Comparison of CMOS to TTL

The components of CMOS are usually more costly than their TTL counterparts. But, from the system level point of view the CMOS technology is less expensive as they require small space and less regulation regarding the physical dimension of the component.

The circuit based on CMOS draw less power in their idle stage in comparison with the TTL based design. But, their power dissipation and consumption may increase at higher clock speed than TTL ones. They draw less current which needs less distribution of power supply and hence, a cheaper and simpler design can be ...