The Evolution of Computer Technology

The Evolution of Computer Technology

Introduction

High performance computing is the demand of time, to improve the system performance computing must be high. Different techniques are used in order to improve the system performance, in which performance of computer's memory system is improved. Latency and bandwidth are generally two attributes of the performance of memory system. Design of several memory systems changes improve at the expanse from on to another and the also improvements certainly impact both latency and bandwidth. Bandwidth normally centers on the greatest achievable steady-state rate of transfer of a memory. Typically this is calculated though running a lengthy unit-stride circle writing or reading the memory. While when a small amount of information such as 32 bit or 64 bit is transferred from processer to memory vice versa is called latency which is measured of the worst case performance of the memory system. Both latency as well as bandwidth is significant part of most high performance applications (Murray, 2006).

Since memory systems are separated into components, and there bandwidth and latency are different. The bandwidth between a CPU and cache will be greater than the range of frequencies between cache and the main memory, for example. There possibly a number of caches and pathways to memory in addition. Typically, the bandwidth of peak memory cited by vendors is the rate between the processor and the data cache (Flynn et.al, 1995).

Discussion

RISC

RISC is reduced instruction set computing and here the thinking is that the design of processor is simpler and probably has a minor footprint, thus permitting for high speed clock, and therefore high speed execution.

RISC or Reduced instruction set computing is actually a design strategy of CPU based on the approach that simplified instructions can offer privileged performance. Enabling the simplicity can execute the instruction much faster. Any computer that is based on the same approach is a computer with a reduced instruction set also known as RISC (Shen et.al, 2005).

A variety of propositions have been completed concerning a precise explanation of RISC, but the common perception is that any system that utilizes a small and highly-optimized instruction set, more willingly than a more particular set of instructions usually found in other sorts of architectures. Reduced instruction set computing systems utilize the store architecture the opposite architecture is recognized as complex instruction set computing (CISC).

Pipelining

Pipelining is an execution procedure where several instructions are overlapped in implementation. ...