[THE IMPACT OF ANALOGUE TO DIGITAL AND DIGITAL TO ANALOGUE CONVERSION]

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The Impact of Analogue to Digital And Digital To Analogue Conversion

In modern ultra-wideband receivers, e.g. of satellite communication systems and software radio, the interface between analogue and digital signal processing is more and more shifted towards the receiver's front end (antenna, optical/electrical interface, etc.). For these ultra-wideband and high-speed applications present-day state-of-the-art single electronic analogue-to-digital converters (ADCs) are often either too slow, or resolve the signal to be quantized too coarsely. Therefore, it is a challenging task to develop extremely fast and yet precisely enough ultra-wideband front-end analogue-to-digital interfaces (ADIs).

For any ADI, the use of a single ultra-fast ADC would represent the most robust and least sensitive approach, if such a device was available. Here, time jitter due to sample-and-hold (S&H) circuit and clock generator represent the major error source in addition to quantization error and overflow saturation (Gockler, 1992, pp. 197).

Constant time delay, gain error and DC-offset have no influence for many applications especially in communications. In case of too low resolution, the single ADC can be approximated by a parallel connection of a concurrent ADCs, where each output sample is given by the arithmetic mean over the a samples nominally taken at the same time instant. A feasible way to increase the maximum ADI sampling rate f S is a parallel connection of b by the factor of b slower time-interleaved ADCs (TI-ADCs). Unfortunately, mismatch of the parallel TI-ADC branches (different gain, time delay, DC-offset, etc.) give rise to severe deteriorations. This problem can, however, be overcome by the hybrid ADC (HADC) that combines the TI-ADC and multiple concurrent ADC (MC-ADC) approaches in such a manner that each of the ADCs of the TI approach is replaced with an MC-ADC, where each MC-ADC comprises the same number of ADCs.

The drawbacks of this approach are the higher power consumption and chip area as a consequence of the higher number M ¼ ab of ADCs required. For these four baseline approaches a comprehensive error analysis taking into account gain error, time delay, DC-offset, quantisation error, overflow saturation, and time jitter due to sample-and-hold (S&H) circuit(s) and clock generator(s), is available only for the MC-ADC .

In error analyses of single ultrafast ADC, either the impact of quantisation error and overflow saturation or of time jitter on signal-to-noise and distortion ratio (SNDR) is considered exclusively. For TI-ADC only the influence of gain errors, time delays and DC-offsets are well investigated. For example, a combined error analysis of these three error sources can be found in (Gustavsson, 2000, pp. 114), where explicit and expected expressions for the SNDR are given. In the present paper, a comprehensive parametric error model of ADC is developed, which can likewise be applied to investigate the features and performance of each of the four ADC approaches introduced above. This error model is used to compare the four baseline systems for ADC, which can be applied to any ADC technology.

The parametric error model is composed ...